For performance enhancement of semiconductor large-scale integrated (LSI) circuits, it is indispensable to improve performances of field effect transistors (FETs) which are for use as basic on-chip circuit device. Until today, the circuit-device performance improvement has been progressed by miniaturization, i.e., onchip device scaling.
As FETs become shorter in channel length due to the miniaturization, the electrical resistance of a channel decreases. Accordingly, the resistance of portions other than the channel such as source and drain electrodes, known as the parasitic resistance, exerts a great influence on the performance of circuit elements. Thus, in order to achieve further miniaturization, it is a must to reduce the parasitic resistance. For example, in FETs which are formed on a bulk silicon (Si), about the half of a parasitic resistance component arises from electrical contact resistance at a contact portion between Si and an electrode metal. Therefore, reducing the contact resistance is an effective means in order to reduce the parasitic resistance. A problem similar to that of the source/drain electrodes in FETs occurs for highly miniaturized contact electrodes also.
At the interface between electrode metal and semiconductor, e.g., Si, what is called the Schottky barrier takes place. This becomes the origin of electrical contact resistance. To reduce the contact resistance, two approaches are currently available which follow.
The first approach is to increase the impurity concentration near the interface on the silicon side. By increasing the impurity concentration, the width of a depletion layer becomes smaller, resulting in the Schottky barrier being thinned. Thus, the effective Schottky barrier is reduced by the so-called mirror image effect thus induced. However, it is theoretically incapable of increasing the activation impurity concentration to the extent that it is greater than a limit of solid solubility. Further, the density of a practically activatable impurity stays lower than the solid solubility limit, and therefore this method is considered to have its limits.
The second approach is to use Schottky barrier height-lowered material as the electrode metal material. The Schottky barrier for electrons at an interface between Si and nickel mono-silicide (NiSi), which is considered to be one of next-generation electrode materials, has a relatively high value of 0.65 electron-volts (eV). When platinum (Pt) is added in order to increase the thermal immunity of NiSi, the Schottky barrier for electrons becomes much higher. On the contrary, if the electrode metal material is replaced by silicides of a rare earth metal, e.g., erbium (Er) or else, the Schottky barrier for electrons decreases to about 0.4 eV. According to generally known Schottky barrier theories, an electrical current flowing in Schottky barrier varies exponentially with respect to the height of Schottky barrier. Accordingly, lowering the Schottky barrier height results in significant improvement of electrical contact resistance between the electrode and semiconductor.
From a viewpoint of the second method, advances are presently made in studies of a new metal silicide material in place of the NiSi. In particular, for n-channel type metal insulator semiconductor field effect transistors (nMISFETs), rare earth metal silicides have attracted much attention, which are inherently low in Schottky barrier height with respect to electrons.
However, the advantage of lowering the Schottky barrier height in nMISFETs does not come without accompanying a penalty: an increase in Schottky barrier height for holes in p-type MISFETs. In order to avoid this risk, a need is felt to use for pMISFETs a different kind of electrode material from that for nMISFETs, such as NiSi, Pt-added NiSi or PtSi, which is extra-low in Schottky barrier for holes. This is known as the “dual silicide” structure.
In contrast, in order to adjust a voltage drop (Vf) of Schottky diode in the forward direction, a technique is known which uses for an electrode two kinds of metals that are different in Vf characteristics from each other. An example of it is disclosed in U.S. Pat. No. 6,972,470 B2.
Additionally, it has been reported that the interface with silicon can decrease in morphology in cases where erbium silicide (ErSi) is used for electrodes. Regarding this phenomenon, detailed teachings are found, for example, in S. S. Lau et al., “Surface morphology of erbium silicide,” Applied Physics Letter 41(1), pp. 77-80 (1982).
As previously stated, in order to reduce electrical contact resistance at the source and drain electrodes of an nMISFET, it is desirable to use specific electrode material which is less in Schottky barrier with respect to electrons serving as majority carriers of the nMISFET. On the contrary, to reduce contact resistance at the source and drain electrodes of a pMISFET, it is needed to use another electrode material that is less in Schottky barrier for holes acting as the carriers of such pMISFET. When an attempt is made to use such different electrode materials for nMISFET and pMISFET, a need arises for separately forming, by different processes, the electrodes for nMISFET and those for pMISFET. This poses a problem as to an increase in process complexity. A similar problem also occurs when forming on a semiconductor device both a contact electrode associated with an n-type diffusion layer which uses electrons as its majority carriers and a contact electrode with a p-type diffusion layer which uses holes as its carriers.